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march 2006 rev 1 1/28 28 vnd5050j-e VND5050K-E double channel high side driv er with analog current sense for automotive applications features general (*) typical value with all loads connected application all types of resistive, inductive and capacitive loads main inrush current active management by power limitation very low stand-by current 3.0v cmos compatible input optimized electromagnetic emission very low electromagnetic susceptibility in compliance with the 2002/95/ec european directive diagnostic functions open drain status output on state open load detection off state open load detection thermal shutdown indication protections undervoltage shut-down overvoltage clamp output stuck to v cc detection load current limitation self limiting of fast thermal transients protection against loss of ground and loss of v cc thermal shut down reverse battery protection (see figure 28 ) electrostatic discharge protection description the VND5050K-E and vnd5050j-e is a monolithic device made using stmicroelectronics vipower m0-5 technology. it is intended for driving resistive or inductive loads with one side connected to ground. active v cc pin voltage clamp protects the device against low energy spikes (see iso7637 transient compatibility table). the device detects open load condition both in on and off state, when stat_dis is left open or driven low. output shorted to v cc is detected in the off state. when stat_dis is driven high, status pin is in high impedance state. output current limitation protects the device in overload condition. in case of long overload duration, the device limits the dissipated power to safe level up to thermal shut-down intervention. thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears.. powersso-24 powersso-12 order codes max supply voltage v cc 41v operating voltage range v cc 4.5 to 36v max on-state resistance (per ch.) r on 50 m ? current limitation (typ) i limh 19 a off state supply current i s 2 a (*) package part number (tube) part number (tape & reel) powersso-12 vnd5050j-e vnd5050j-e13tr powersso-24 VND5050K-E VND5050K-E13tr www.st.com
contents vnd5050j-e / VND5050K-E 2/28 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 gnd protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16 3.1.1 solution 1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1.2 solution 2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 c i/os protection: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 open load detection in off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 powersso-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 powersso-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
vnd5050j-e / VND5050K-E block diagram and pin description 3/28 1 block diagram and pin description figure 1. block diagram name function figure 2. configuration diagram (top view) & suggested connections for unused and n.c. pins overtemp. 1 v cc gnd logic driver 1 v cc clamp undervoltage clamp 1 openload on 1 current limiter 1 openload off 1 control & protection equivalent to channel1 input2 status2 v cc input2 status2 input1 status1 output1 output2 stat_dis pwr lim 1 table 1. pin function v cc battery connection outputn power output gnd ground connection. must be reverse battery protected by an external diode/resistor network inputn voltage controlled input pin with hysteresis, cmos compatible. controls output switch state statusn open drain digital diagnostic pin stat_dis active high cmos compatible pin, to disable the status pin connection / pin status n.c. output input stat_dis floating x x x x x to ground n.r. x n.r. 10k ? resistor 10k ? resistor n.r. = not recommended powersso-12 powersso-24 input1 status1 gnd. v cc n.c. stat_dis n.c. v cc status2 n.c. n.c. input2 output1 output1 output1 output1 output1 output1 output2 output2 output2 output2 output2 output2 tab = v cc tab = v cc v cc output 1 output 2 output 2 v cc output 1 12 11 10 9 8 7 1 2 3 4 5 6 input 2 gnd input 1 status 1 stat_dis status 2
electrical specifications vnd5050j-e / VND5050K-E 4/28 2 electrical specifications figure 3. current and voltage conventions 2.1 absolute maximum ratings symbol parameter value unit v fn = v outn - v ccn during reverse battery condition i gnd v cc gnd outputn stat_dis i sd inputn i inn v sd v inn i outn v outn statusn i statn v statn v cc i s table 2. absolute maximum ratings v cc dc supply voltage 41 v - v cc reverse dc supply voltage 0.3 v - i gnd dc reverse ground pin current 200 ma i out dc output current internally limited a - i out reverse dc output current 15 a i in dc input current +10 / -1 ma i stat dc status current +10 / -1 ma i stat_dis dc status disable current +10 / -1 ma e max maximum switching energy (l=1.5mh; r l =0 ? ; v bat =13.5v; t jstart =150oc; i out = i liml (typ.) ) 51 mj v esd electrostatic discharge (human body model: r=1.5k ?; c=100pf) - input - status - stat_dis - output - v cc 4000 4000 4000 5000 5000 v v v v v v esd charge device model (cdm-aec-q100-011) 750 v t j junction operating temperature -40 to 150 c t stg storage temperature - 55 to 150 c
vnd5050j-e / VND5050K-E electrical specifications 5/28 2.2 thermal data symbol parameter value unit powersso-12 powersso-24 2.3 electrical characteristics 8v electrical specifications vnd5050j-e / VND5050K-E 6/28 symbol parameter test conditions min typ max unit symbol parameter test conditions min. typ. max. unit w on switching energy losses during t won r l =6.5 ? (see figure 5 )0.21mj w off switching energy losses during t woff r l =6.5 ? (see figure 5 )0.28mj table 5. switching (v cc =13v) (continued) symbol parameter test conditions min. typ. max. unit table 6. status pin (v sd =0v) v stat status low output voltage i stat = 1.6 ma, v sd =0v 0.5 v i lstat status leakage current normal operation or v sd =5v, v stat = 5v 10 a c stat status pin input capacitance normal operation or v sd =5v, v stat = 5v 100 pf v scl status clamp voltage i stat = 1ma i stat = - 1ma 5.5 -0.7 7v v table 7. protections (1) i limh dc short circuit current v cc =13v 5vt tsd (see figure 4 )20 s v demag turn-off output voltage clamp i out =2a; v in =0; l=6mh v cc -41 v cc -46 v cc -52 v v on output voltage drop limitation i out =0.1a; t j = -40c...+150c (see figure 6 ) 25 mv (1) to ensure long term reliability under heavy overload or short circ uit conditions, protection and related diagnostic signals must be used together with a proper software strategy. if the dev ice is subjected to abnormal c onditions, this software must limit the duration and number of activation cycles
vnd5050j-e / VND5050K-E electrical specifications 7/28 symbol parameter test conditions min typ max unit symbol parameter test conditions min. typ. max. unit table 8. openload detection i ol openload on state detection threshold v in = 5v ,8v electrical specifications vnd5050j-e / VND5050K-E 8/28 figure 4. status timings conditions input output sense (v csd =0v) (1) table 10. truth table (1) if the v csd is high, the sense output is at a high impedance, its potential depends on leakage currents and external circuit. normal operation l h l h h h current limitation l h l x h h overtemperature l h l l h l undervoltage l h l l x x output voltage > v ol l h h h l (2) h (2) the status pin is low with a delay equal to tdstkon after input falling edge. output current < i ol l h l h h (3) l (3) the status pin becomes high with a delay equal to tpol after input falling edge. v in v stat t pol open load status timing (without external pull-up) i out < i ol v out < v ol t dol(on) v in v stat open load status timing (with external pull-up) i out < i ol v out > v ol t dol(on) v in v stat over temp status timing t sdl t sdl t j > t tsd v in v stat t dstkon output stuck to v cc i out > i ol v out > v ol t dol(on)
vnd5050j-e / VND5050K-E electrical specifications 9/28 figure 5. switching characteristics figure 6. output voltage drop limitation v out dv out /dt (on) t r 80% 10% t f dv out /dt (off) t d(off) t d(on) input t t 90% v on i out v cc -v out t j =150 o c t j =25 o c t j =-40 o c v on /r on(t)
electrical specifications vnd5050j-e / VND5050K-E 10/28 table 11. electrical transient requirements (1) for load dump exceeding the above value a centralized suppressor must be adopted. iso 7637-2: 2004(e) test pulse test levels number of pulses or test times burst cycle/pulse repetition time delays and impedance iii iv 1 -75v -100v 5000 pulses 0.5 s 5 s 2 ms, 10 : 2a +37v +50v 5000 pulses 0.2 s 5 s 50 p s, 2 : 3a -100v -150v 1h 90 ms 100 ms 0.1 p s, 50 : 3b +75v +100v 1h 90 ms 100 ms 0.1 p s, 50 : 4 -6v -7v 1 pulse 100 ms, 0.01 : 5b (1) +40v +40v 1 pulse 400 ms, 2 : iso 7637-2: 2004(e) test pulse test level results iii iv 1c c 2a c c 3a c c 3b c c 4c c 5b (1) cc class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device are not perf ormed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
vnd5050j-e / VND5050K-E electrical specifications 11/28 figure 7. waveforms status input normal operation undervoltage v cc v usd v usdhyst input status load current load current stat_dis stat_dis undefined open load without external pull-up status input status input open load with external pull-up load voltage load voltage v ol v out >v ol stat_dis stat_dis load current i out v ol stat_dis i out >i ol t dstkon t pol overload operation input status t tsd t r t j load current stat_dis t rs i limh i liml thermal cycling power limitation current limitation shorted load normal load
electrical specifications vnd5050j-e / VND5050K-E 12/28 2.4 electrical characteristics curves figure 8. off state output current figure 9. high level input current figure 10. input clamp voltage figure 11. input high level figure 12. input low level figure 13. input hysteresis voltage -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 0.125 0.25 0.375 0.5 0.625 0.75 0.875 1 iloff1 (ua) off state vcc=13v vin=vout=0v -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 lih (ua) vin=2.1v -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 6 6.25 6.5 6.75 7 7.25 7.5 7.75 8 vicl (v) lin=1ma -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 0.5 1 1.5 2 2.5 3 3.5 4 vih (v) -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 0.5 1 1.5 2 2.5 3 3.5 4 vil (v) -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 vihyst (v)
vnd5050j-e / VND5050K-E electrical specifications 13/28 figure 14. status low output voltage figure 15. on state resistance vs t case figure 16. status leakage current figure 17. on state resistance vs v cc figure 18. status clamp voltage figure 19. openload on state detection threshold -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 vstat (v) istat=1.6ma -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 10 20 30 40 50 60 70 80 90 100 ron (mohm) iout=2a vcc=13v -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0.025 0.03 0.035 0.04 0.045 0.05 0.055 ilstat (ua) vstat=5v 0 5 10 15 20 25 30 35 40 vcc (v) 0 10 20 30 40 50 60 70 80 90 100 ron (mohm) tc= 150c tc= 125c tc= 25c tc= -40c -50 -25 0 25 50 75 100 125 150 175 tc ( c) 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 vscl (v) istat=1ma -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 10 20 30 40 50 60 70 80 90 100 iol (ma) vin=5v
electrical specifications vnd5050j-e / VND5050K-E 14/28 figure 20. openload off state voltage detection threshold figure 21. i lim vs t case figure 22. turn-on voltage slope figure 23. undervoltage shutdown figure 24. turn-off voltage slope figure 25. stat_dis clamp voltage -50 -25 0 25 50 75 100 125 150 175 tc ( c) 1 1.5 2 2.5 3 3.5 4 4.5 5 vol (v) vin=0v -50 -25 0 25 50 75 100 125 150 175 tc ( c) 5 7.5 10 12.5 15 17.5 20 22.5 25 ilimh (a) vcc=13v -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 100 200 300 400 500 600 700 800 900 1000 dvout/dt(on) (v/ms) vcc=13v ri=6.5ohm -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 2 4 6 8 10 12 14 vusd (v) -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 100 200 300 400 500 600 700 800 900 1000 dvout/dt(off) (v/ms) vcc=13v ri=6.5ohm -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 2 4 6 8 10 12 14 vsdcl(v) isd=1ma
vnd5050j-e / VND5050K-E electrical specifications 15/28 figure 26. high level stat_dis voltage figure 27. low level stat_dis voltage -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 1 2 3 4 5 6 7 8 vsdh(v) -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 1 2 3 4 5 6 7 8 vsdl(v)
application information vnd5050j-e / VND5050K-E 16/28 3 application information figure 28. application schematic 3.1 gnd protection networ k against reverse battery 3.1.1 solution 1: resistor in the ground line (r gnd only). this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1. r gnd d 600mv / (i s(on)max ). 2. r gnd t v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsds. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not shared by the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on how ma ny devices are on in the case of several high side drivers sharing the same r gnd . v cc gnd output d gnd r gnd d ld p c +5v v gnd stat_dis input r prot r prot r prot +5v status note: channel 2 has the same internal circuit as channel 1.
vnd5050j-e / VND5050K-E application information 17/28 if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then st suggest s to utilize solution 2 (see below). 3.1.2 solution 2: a diode (d gnd ) in the ground line. a resistor (r gnd =1k : should be inserted in parallel to d gnd if the device drives an inductive load. this small signal diode can be safely shared amongst several different hsds. also in this case, the presence of the grou nd network will produce a shift ( | 600mv) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. this shift will not vary if more than one hsd shares t he same diode/resistor network. 3.2 load dump protection d ld is necessary ( voltage transient suppressor ) if the load dump peak voltage exceeds the v cc max dc rating. the same applies if the device is subject to transients on the v cc line that are greater than the ones shown in the iso 7637-2: 2004(e) table. 3.3 c i/os protection: if a ground protection network is used and negative transient are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of p c and the current required by the hsd i/os (input levels compatibilit y) with the latch-up limit of p c i/os. -v ccpeak /i latchup d r prot d (v oh p c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100v and i latchup t 20ma; v oh p c t 4.5v 5k : d r prot d 180k : . recommended values: r prot =10k : , c ext =10nf. 3.4 open load detection in off state off state open load detection requires an external pull-up resistor (r pu ) connected between output pin and a positive supply voltage (v pu ) like the +5v line used to supply the microprocessor. the external resistor has to be selected according to the following requirements: 1. no false open load indication when load is connected: in this case we have to avoid v out to be higher than v olmin ; this results in the following condition v out =(v pu /(r l +r pu ))r l application information vnd5050j-e / VND5050K-E 18/28 because i s(off) may significantly increase if v out is pulled high (up to several ma), the pull- up resistor r pu should be connected to a supply that is switched off when the module is in standby. the values of v olmin , v olmax and i l(off2) are available in the electrical characteristics section. figure 29. open load detection in off state v ol v batt. v pu r pu r l r driver + logic + - input status v cc out ground i l(off2)
vnd5050j-e / VND5050K-E package and pcb thermal data 19/28 4 package and pcb thermal data 4.1 powersso-12 thermal data figure 30. powersso-12 pc board figure 31. r thj-amb vs. pcb copper area in open box free air condition figure 32. powersso-12 thermal impedance junction ambient single pulse pulse calculation formula z th r th z thtp 1 ? () + ? = where = t p /t layout condition of r th and z th measurements (pcb: double layer, thermal vias, fr4 area= 77mm x 86mm, pcb thickness=1.6mm, cu thickness=70m (front and back side), copper areas: from minimum pad lay-out to 8cm 2 ). 40 45 50 55 60 65 70 0246810 rthj_amb(c/w) pcb cu heatsink area (cm^2) 0.1 1 10 100 1000 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zt h (? c/w) footprint 8 cm 2 2 cm 2
package and pcb thermal data vnd5050j-e / VND5050K-E 20/28 figure 33. thermal fitting model of a double channel hsd in powersso-12 thermal parameter area/island (cm 2 )footprint2 8 r1=r7 (c/w) 0.7 r2=r8 (c/w) 2.8 r3 (c/w) 7 r4 (c/w) 10 10 9 r5 (c/w) 22 15 10 r6 (c/w) 26 20 15 c1=c7 (w.s/c) 0.001 c2=c8 (w.s/c) 0.0025 c3 (w.s/c) 0.05 c4 (w.s/c) 0.2 0.1 0.1 c5 (w.s/c) 0.27 0.8 1 c6 (w.s/c) 3 6 9
vnd5050j-e / VND5050K-E package and pcb thermal data 21/28 4.2 powersso-24 thermal data figure 34. powersso-24 pc board figure 35. r thj-amb vs. pcb copper area in open box free air condition figure 36. powersso-24 thermal impedance junction ambient single pulse pulse calculation formula z th r th z thtp 1 ? () + ? = where = t p /t layout condition of r th and z th measurements (pcb: double layer, thermal vias, fr4 area= 77mm x 86mm, pcb thickness=1.6mm, cu thickness=70 m (front and back side), copper areas: from minimum pad lay-out to 8cm 2 ). 30 35 40 45 50 55 0246810 rthj_amb(c/w) pcb cu heatsink area (cm^2) 0.1 1 10 100 1000 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (?c/w) footprint 8 cm 2 2 cm 2
package and pcb thermal data vnd5050j-e / VND5050K-E 22/28 figure 37. thermal fitting model of a single channel hsd in powersso-12 thermal parameter area/island (cm 2 )footprint2 8 r1=r7 (c/w) 0.4 r2=r8 (c/w) 2 r3 (c/w) 6 r4 (c/w) 7.7 r5 (c/w) 9 9 8 r6 (c/w) 28 17 10 c1=c7 (w.s/c) 0.001 c2=c8 (w.s/c) 0.0022 c3 (w.s/c) 0.025 c4 (w.s/c) 0.75 c5 (w.s/c) 1 4 9 c6 (w.s/c) 2.2 5 17
vnd5050j-e / VND5050K-E package information 23/28 5 package information in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second-level interconnect. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. symbol millimeters min typ max 5.1 package mechanical figure 38. powersso-12? package dimensions table 12. powersso-12? mechanical data a 1.250 1.620 a1 0.000 0.100 a2 1.100 1.650 b 0.230 0.410 c 0.190 0.250 d 4.800 5.000 e 3.800 4.000 e0.800 h 5.800 6.200 h 0.250 0.500 l 0.400 1.270 k0 8 x 1.900 2.500 y 3.600 4.200 ddd 0.100 16 12 7 gauge plane 0.25 mm seating plane bottom view h x 45? d c l e e h y x b a a2 c a1 k c ddd
package information vn d5050j-e / VND5050K-E 24/28 figure 39. powersso-24? package dimensions symbol millimeters min typ max table 13. powersso-24? mechanical data a 2.15 2.47 a2 2.15 2.40 a1 0 0.075 b 0.33 0.51 c 0.23 0.32 d 10.10 10.50 e7.4 7.6 e0.8 e3 8.8 g 0.1 g1 0.06 h 10.1 10.5 h 0.4 l 0.55 0.85 n 10deg x4.1 4.7 y6.5 7.1
vnd5050j-e / VND5050K-E package information 25/28 5.2 packing information figure 40. powersso-12 tube shipment (no suffix) figure 41. powersso-12 tape and reel shipment (suffix tr) all dimensions are in mm. base q.ty 100 bulk q.ty 2000 tube length ( 0.5) 532 a1.85 b6.75 c ( 0.1) 0.6 a c b base q.ty 2500 bulk q.ty 2500 a (max) 330 b (min) 1.5 c ( 0.2) 13 f20.2 g (+ 2 / -0) 12.4 n (min) 60 t (max) 18.4 reel dimensions tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 12 tape hole spacing p0 ( 0.1) 4 component spacing p 8 hole diameter d ( 0.05) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.1) 5.5 compartment depth k (max) 4.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed
package information vn d5050j-e / VND5050K-E 26/28 figure 42. powersso-24 tube shipment (no suffix) figure 43. powersso-24 tape and reel shipment (suffix tr) a c b all dimensions are in mm. base q.ty 49 bulk q.ty 1225 tube length ( 0.5) 532 a 3.5 b 13.8 c ( 0.1) 0.6 base q.ty 1000 bulk q.ty 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 24.4 n (min) 100 t (max) 30.4 reel dimensions tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 24 tape hole spacing p0 ( 0.1) 4 component spacing p 12 hole diameter d ( 0.05) 1.55 hole diameter d1 (min) 1.5 hole position f ( 0.1) 11.5 compartment depth k (max) 2.85 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed
vnd5050j-e / VND5050K-E revision history 27/28 6 revision history date revision changes table 14. document revision history 30-mar-2006 1 initial release.
vnd5050j-e / VND5050K-E 28/28 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorize representative of st, st products are not designed, authorized or warranted for use in military, air craft, space, life saving, or li fe sustaining applications, nor in products or systems, where failure or malfunction may result in personal injury, death, or severe property or environmental damage. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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